-- $Id: $mg84
-- File name:   MIU.vhd
-- Created:     11/29/2010
-- Author:      Cody Farmer
-- Lab Section: 337-004
-- Version:     1.0  Initial Design Entry
-- Description: MIU.


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
entity MIU is
  port(
    nRE : in std_logic;
    nWE : in std_logic;
    memDataRead : out std_logic_vector(7 downto 0);
    memDataWrite : in std_logic_vector(7 downto 0);
    nReadEnable : out std_logic;
    nWriteEnable : out std_logic;
    Databus : inout std_logic_vector(7 downto 0)
  );
end MIU;

architecture dataflow of MIU is
begin
  nReadEnable <= nRE;
  nWriteEnable <= nWE;
  memDataRead <= Databus when (not(nWE) and nRE) = '1' else (others => 'Z');
  Databus <= memDataWrite when (nWE AND not(nRE)) = '1' else (others => 'Z');
end dataflow;
